Motorola DSP96002 User Manual page 10

an "early write" signal for DRAM interfacing. R/
for a write access. The R/
put, R/
the external bus is not used during an instruction cycle. R/
hardware reset.
— –
B S (Bus Strobe) - three-state, active low output when a bus master, three-stated when not
a bus master. Asserted at the start of a bus cycle (providing an "early bus start" signal
for DRAM interfacing) and deasserted at the end of the bus cycle. The early negation
provides an "early bus end" signal useful for external bus control. If the external bus is
not used during an instruction cycle,
bus cycle.
— –
T T (Transfer Type) - three-state, active low output when a bus master, three-stated when
not a bus master. When a bus master,
(see Section seven).
column, nibble or serial shift register) is detected. If the external bus is not used during
an instruction cycle or a fault is detected by the page circuit during an external access,
— –
T
programmable.
— –
T S (Transfer Strobe) - three-state, active low output when a bus master, active low input
when not a bus master. When a bus master,
dress lines A0-A31, S1, S0,
bus write transfer is taking place. During a read cycle, input data is latched inside the
DSP96002 on the rising edge of
the data bus after
control for external data bus buffers if they are present. If the external bus is not used
during an instruction cycle,
An external flip-flop can delay
coding time. The
able the data bus output drivers during host read operations and to latch data inside the
Host Interface during host write operations. As an input,
nous relative to the input clock. Write data is latched inside the Host Interface on the
rising edge of
MOTOROLA
—
—
W may change asynchronous relative to the input clock. R/
— –
B S is three-stated during hardware reset.
— –
T T is asserted when a fast access memory mode (page, static
T remains deasserted. The parameters of the page circuit fault detection are user
— –
T T is three-stated during hardware reset.
—
— –
T S is asserted. Therefore
—
— –
T S pin is also the Host Interface transfer strobe input used to en-
— – — –
T S. T S is three-stated during hardware reset.
DSP96002 USER'S MANUAL
—
W is high for a read access and is low
W pin is also the Host Interface read/write input. As an in-
— –
B S remains deasserted until the next external
— –
T T is controlled by an on-chip page circuit
— –
T S is asserted to indicate that the ad-
– — – —
B S, B L and R/ W are stable and that a bus read or
— –
T S. During a write cycle, output data is placed on
— –
T S can be used as an output enable
–
T S remains deasserted until the next external bus cycle.
— –
T S if required for slow devices or more address de-
—
W goes high if
—
W is three-stated during
— –
T S may change asynchro-
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