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B.1.54
[NxN] by [NxN] Matrix Multiplication (Modulo-Aligned)
;This routine performs an [NxN] by [NxN] matrix multiplication
;for the 96000 floating-point DSP chip.
;for N=4.
;format.
For example, take the matrix A:
;
;
;
;
;
;
;Matrix A's elements are stored as such:
;amatrix
dc A(1,1),A(1,2),...,A(1,N),A(2,1),A(2,2),...,A(2,N), ...
;
;Matrices A and C are in X memory, while matrix B is in Y memory.
;Since modulo N**2 addressing is used for all matrices, the first
;k least significant bits of the address of the beginning of any
;matrix storage area must be equal to zero, where 2**k >= N**2.
;
;This routine takes
;
;
16 + n(3 + n(2 +n(1) + 2) + 2)
;
;
= n**3 + 4n**2 + 5n + 16 instruction cycles to complete.
;
;
;
page 132,60,1,1
N
equ 4
N_sqr
equ N*N
org x:$0
amatrix
dc .5,.6,.7,.8
dc .9,.1,.2,.3
dc .4,.5,.6,.7
org x:$20
cmatrix
org y:$0
bmatrix
MOTOROLA
Totals:
The data for all matrices is stored in row major
A(1,1) ... A(1,N)
.
.
A(N,1) ... A(N,N)
dc .1,.2,.3,.4
ds N_sqr
dc .5,.5,.5,.5
DSP96002 USER'S MANUAL
44
8N+37
Sample data is given
.
.
.
.
Program ICycles
Words
B-127
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