Motorola DSP96002 User Manual page 364

FTRAPcc Conditional Software Interrupt
Operation:
If cc, then begin software exception processing.
Description:
If the specified floating-point condition is true, normal instruction execution is suspended and software ex-
ception processing is initiated. The interrupt priority level (I1,I0) is set to 3 in the status register if a long
interrupt service routine is used. If the specified condition is false, continue with the next instruction. See
Section A.10 for restrictions. Non-aware floating-point conditions set the SIOP flag in the IER register and
the UNCC bit in the ER register if the NAN bit is set. This action occurs before stacking the status register
when the specified non-aware floating-point condition is true.
"cc" may specify the following conditions:
Mnemonic
EQ
ERR
GE
GL
GLE
GT
INF
LE
LT
MI
NE(Q)
NGE
NGL
NGLE
NGT
NINF
NLE
NLT
OR
PL
UN
Note: The operands for the ERR condition are taken from the ER register.
* See the description of the UNcc bit in Section A.4.
CCR Condition Codes: Not affected.
ER Status Bits:
A - 176
- equal
- error
- greater than or equal
- greater or less than
- greater, less or equal
- greater than
- infinity
- less than or equal
- less than
- minus
- not equal
- not(greater than or equal)NAN v (N & ~Z) = 1
- not(greater or less than) NAN v Z = 1
- not(greater, less or equal)NAN = 1
- not greater than
- not infinity
- not(less than or equal)
- not less than
- ordered
- plus
- unordered
DSP96002 USER'S MANUAL
Assembler Syntax:
FTRAPcc
Condition
Z = 1
UNCC v SNAN v OPERR v No
OVF v UNF v DZ = 1
NAN v (N & ~Z) = 0
NAN v Z = 0
NAN = 0
NAN v Z v N = 0
I = 1
NAN v ~(N v Z) = 0
NAN v Z v ~N = 0
N = 1
Z = 0
NAN v Z v N = 1
I = 0
NAN v ~(N v Z) = 1
NAN v Z v ~N = 1
NAN = 0
N = 0
NAN = 1
FTRAPcc
Non-aware
Set UNCC*
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
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