Table of Contents
Advertisement
This manual describes the first member of a family of dual-port IEEE floating point programmable CMOS
processors. The family concept defines a core as the Data ALU, Address Generation Unit, Program Con-
troller and associated Instruction Set. The On-Chip Program Memory, Data Memories and Peripherals sup-
port many numerically intensive applications and minimize system size and power dissipation; however,
they are not considered part of the core.
The first family member is the DSP96002. The main characteristics of the DSP96002 are support of IEEE
754 Single Precision (8 bit Exponent and 24 bit Mantissa) and Single Extended Precision (11 bit Exponent
and 32 bit Mantissa) Floating-Point and 32 bit signed and unsigned fixed point arithmetic, coupled with two
identical external memory expansion ports. Its features are listed below.
•
IEEE 745 Standard SP (32-bit) and SEP (44 bit) Arithmetic
•
16.5 Million Instructions per Second (Mips) with a 33 Mhz clock
•
49.5 Million Floating Point Instructions per Second (MFLOPS) peak with a 33 Mhz
clock
•
Single-Cycle 32 x 32 Bit Parallel Multiplier
•
Highly Parallel Instruction Set with Unique DSP Addressing Modes
•
Nested Hardware Do Loops
•
Fast Auto-Return Interrupts
•
2 Independent On-Chip 512 x 32 Bit Data RAMs
•
2 Independent On-Chip 1024 x 32 Bit Data ROMs
•
Off-Chip Expansion to 2 x 2
•
On-Chip 1,024 x 32 Bit Program RAM
•
On-Chip 64 x 32 Bit Bootstrap ROM
•
Off-Chip Expansion to 2
•
Two Identical External Memory Expansion Ports
•
Two 32-Bit Parallel Host MPU/DMA Interfaces
•
On-Chip Two-Channel DMA Controller
•
On-Chip Emulator
MOTOROLA
SECTION 1
DSP96002 INTRODUCTION
DSP96002 Features
32
32-Bit Words of Data Memory
32
32-Bit Words of Program Memory
DSP96002 USER'S MANUAL
1 - 1
Advertisement
Table of Contents
