Motorola DSP96002 User Manual page 200

32-bit digital signal processor
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Mnemonic
ABS
ADD
ADDC1
AND
ANDC
ANDI
ASL
ASR
Bcc
BCHG
BCLR
BFIND
BRA
BRCLR
BRSET
BScc
BSCLR
BSET
BSR
BSSET
BTST
CLR
CMP
CMPG
DEBUGcc
DEC
DO
DOR
ENDDO
EOR
EXT
EXTB
FABS.S
FABS.X
FADD.S
FADD.X
FADDSUB.S
FADDSUB.X
FBcc
FBScc
FCLR
FCMP
FCMPG
FCMPM
FCOPYS.S
SYMBOLS:
A - 12
UNCC NAN SNAN OPERR OVF UNF DZ INX
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* set according to the standard definition by the result
- not affected by the operation
0 cleared
1 set
? set according to the special computation definition by the result of the operation
Figure A-5. ER Exception Bits Computation
DSP96002 USER'S MANUAL
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Special Definitions
Note 9
Note 13
Note 14
Note 15
Note 18
Note 18
Note 2, 3, 4, 5, 7
Note 2, 3, 4, 5, 7
MOTOROLA

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