Motorola DSP96002 User Manual page 719

32-bit digital signal processor
Table of Contents

Advertisement

B.6
STANDARD BENCHMARK SUMMARY
Benchmark
B.1.1
Real Multiply
B.1.2
N Real Multiplies
B.1.3
Real Update
B.1.4
N Real Updates
B.1.5
N Term Real Convolution (FIR)
B.1.6
N Term Real*Complex Convolution
B.1.7
Complex Multiply
B.1.8
N Complex Multiplies
B.1.9
Complex Update
B.1.10 N Complex Updates
B.1.11 N Term Complex Convolution (FIR)
B.1.12 Nth Order Power Series
B.1.13 2nd Order Real Biquad Filter
B.1.14 N Cascaded 2nd Order Biquads
B.1.15 Radix 2 FFT Butterfly
B.1.16 Adaptive True LMS Filter
Adaptive Delayed LMS Filter
B.1.17 FIR Lattice Filter
B.1.18 All Pole IIR Lattice Filter
B.1.19 General Lattice Filter
B.1.20 Normalized Lattice Filter
B.1.21 [1x3 [3x3
[1x4 [4x4
B.1.22 [NxN [NxN
B.1.23 N Point 3x3 2-Dimensional FIR
B.1.24 Table Lookup with Interpolation
B.1.25 Argument Reduction
B.1.26 Non-IEEE Floating-Point Division
No Error Checking
With Divide By Zero Checking
With Divide By Infinity Checking
With Divide By Zero And Infinity
Checking
B.1.27 Multibit Rotates
With Carry, Static
With Carry, Dynamic
Without Carry, Static
Without Carry, Dynamic
B-200
Matrix Multiply
Matrix Multiply
Matrix Multiply
Figure B-1. Standard Benchmark Summary
DSP96002 USER'S MANUAL
56000/1
DSP96000
Word
Icyc
Word
3
3
3
8
2N+7
8
4
4
4
10
2N+9
10
10
1N+12
10
10
2N+9
9
6
6
7
12
4N+9
12
7
7
8
13
4N+10
15
13
5N+9
17
11
4N+8
11
9
2N+8
9
7
7
7
17
4N+16
19
6
6N
4
7
3N+5
7
9
3N+4
12
12
4N+10
14
13
5N+10
14
12
19
3
2
19
N
+7N
19
+5N+8
2
28
10N
29
+7N+12
+8N+13
12
6
7
9
8
10
4
9
4
6
Icyc
3
2N+7
4
2N+9
1N+12
2N+8
7
4N+9
8
4N+12
4N+14
4N+8
2N+8
7
4N+18
4N
3N
2N
3N+5
3N+7
4N+12
5N+11
12
19
3
2
N
+7N
+6N+7
2
10N
12
6
7
9
8
10
4
9
4
6
MOTOROLA

Advertisement

Table of Contents
loading

Table of Contents