Instruction Timing - Motorola DSP96002 User Manual

A.9

INSTRUCTION TIMING

Figure A-7 shows the number of words and the number of clock cycles required for instruction execution.
The symbols used reference other tables to complete the instruction word and cycle count. The number
of words per instruction is dependent on the addressing mode and the type of parallel data bus move op-
eration specified. The number of execution clock cycles per instruction is dependent on many factors, in-
cluding the number of words per instruction, the addressing mode, whether the instruction fetch pipe is full
or not, whether the Data ALU is operating in the IEEE mode, the number of external bus accesses and
the number of wait states inserted in each external access. The following tables assume:
1. All instruction cycles are counted in clock oscillator cycles.
2. The instruction fetch pipeline is full.
3. There is no contention for instruction fetches.
4. There are no wait states for instruction fetches done sequentially (as for non-change-of-flow in-
structions), but they are taken into account for branch instructions (JMP, Jcc, RTI, etc.).
MOTOROLA
Mnemonic
ABS
ADD
ADDC
AND
ANDC
ANDI
ASL
ASL #shift
ASR
ASR #shift
Bcc
BCHG
BCLR
BFIND
BRA
BRCLR
BRSET
Mnemonic
Figure A-7 Instruction Timing Summary
DSP96002 USER'S MANUAL
Words Cycles
1 + mv 2 + mv
1 + mv 2 + mv
1 + mv 2 + mv
1 + mv 2 + mv
1 + mv 2 + mv
1 2
1 + mv 2 + mv
1 2
1 + mv 2 + mv
1 2
1 + ea 6 + jx
1 + ea 4 + mvb
1 + ea 4 + mvb
1 + mv 2 + mv
1 + ea 6 + jx
2 8 + jx
2 8 + jx
Words Cycles
A - 313