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rupt request will occur if HYRP is set. The starting address of this interrupt is shown in Figure 7-13. HYRE
is cleared by HW/SW reset.
7.4.8.13 HCR Host Y Memory Write Interrupt Enable (HYWE) Bit 13
The Host Y Memory Write Interrupt Enable (HYWE) bit is used to enable the Y Memory Write interrupt when
the Host Y Memory Write Command Pending (HYWP) status bit in the Host Status Register (HSR) is set.
When HYWE is cleared, HYWP interrupts are disabled. When HYWE is set, the Host Y Memory Write in-
terrupt request will occur if HYWP is set. The starting address of this interrupt is shown in Figure 7-13.
HYWE is cleared by HW/SW reset.
7.4.9 Host Status Register (HSR) – DSP96002 Side
The Host Status register (HSR) is a 32-bit read-only status register used by the DSP96002 to interrogate
status and flags of the HI. It cannot be directly accessed by the host processor.
7.4.9.1
HSR Host Receive Data Full (HRDF) Bit 0
The Host Receive Data Full (HRDF) bit indicates that the Host Receive Data register (HRX) contains data
from the host processor, written by the host processor via the host function "TX register write" only. HRDF
is set when the data is transferred from the TX register to the HRX register. HRDF is cleared when the Re-
ceive Data register HRX is read by the DSP96002. HRDF is cleared by INIT (TREQ=1), HOST reset, and
HW/SW reset.
7.4.9.2
HSR Host Transmit Data Empty (HTDE) Bit 1
The Host Transmit Data Empty (HTDE) bit indicates that the Host Transmit Data register (HTX) is empty
and can be written by the DSP96002. HTDE is set when the HTX register is transferred to the RX register.
HTDE is cleared when the Transmit Data register HTX is written by the DSP96002. HTDE is set by INIT
(RREQ=1), HOST reset, and HW/SW reset.
7.4.9.3
HSR Host Command Pending (HCP) Bit 2
The Host Command Pending (HCP) bit indicates that the host processor has set the HC bit and that a Host
Command Interrupt is pending. The HCP bit reflects the status of the HC bit in the Command Vector Reg-
ister (CVR). HC and HCP are cleared by the DSP96002 exception hardware when the second vector loca-
tion of the Host Command interrupt is fetched. HCP is cleared by HW/SW reset.
7.4.9.4
HSR Host Flag 0 (HF0) Bit 3
The Host Flag 0 (HF0) bit indicates the state of Host Flag 0 (HF0) in the Interrupt Control Register ICS. HF0
can only be changed by the host processor. HF0 is cleared by HW/SW reset.
7.4.9.5
HSR Host Flag 1 (HF1) Bit 4
The Host Flag 1 (HF1) bit indicates the state of Host Flag 1 (HF1) in the Interrupt Control Register ICS. HF1
can only be changed by the host processor. HF1 is cleared by HW/SW reset.
MOTOROLA
DSP96002 USER'S MANUAL
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