Motorola DSP96002 User Manual page 211

32-bit digital signal processor
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ANDC
Logical AND with Complement
Operation:
D.L & ~S.L
D.L
(parallel data bus move)
Description:
Logically AND the low portion of D with the logical complement of the low portion of S, and store the result
in the low portion of D.
Input Operand(s) Precision: 32-bit integer.
Output Operand Precision: 32-bit integer.
CCR Condition Codes:
C
- Not affected.
V
- Always cleared.
Z
- Set if result is zero. Cleared otherwise.
N
- Set if result is negative. Cleared otherwise.
I
- Not affected.
LR - Not affected.
R - Not affected.
A
- Not affected.
ER Status Bits:
Not affected.
IER Flags:
Not affected.
Instruction Format: AND
31
DATA BUS MOVE FIELD
OPTIONAL EFFECTIVE ADDRESS EXTENSION OR IMMEDIATE LONG DATA
MOTOROLA
Assembler Syntax:
ANDC
S,D
(move syntax - see the MOVE instruction description.)
DSP96002 USER'S MANUAL
S,D
(move syntax - see the MOVE instruc-
tion description.)
14 13
11
0sss
ANDC
0
1000
1ddd
A - 23

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