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MOTOROLA
SEMICONDUCTOR
TECHNICAL DATA
Addendum to
DSP96002 Digital Signal Processor User Manual
THE DSP96002 INSTRUCTION CACHE and
32-BIT TIMER/EVENT COUNTER
FOREWORD
This document is an addendum to the DSP96002 IEEE Floating-Point Dual-Port Proces-
sor User's Manual (DSP96002UM/AD). It describes significant new features added to the
DSP96002 functionality, including an instruction cache, a new integer mode of operation
and new parallel integer instructions to support it, data ALU register file decoupling, en-
hancements to the OnCE, and a new timer/event counter.
The revised DSP96002 is fully compatible with its predecessor. Special mode bits in var-
ious registers allow the user to access the new features.
This addendum describes each of the features in detail. Section 2 introduces the Instruc-
tion Cache. Section 3 describes the new integer mode and its associated parallel integer
instructions. Section 4 presents presents the single precision mode. Section 5 introduces
enhancements to the On Chip Emulation (OnCE) module. Section 6 describes the new
timer/event counter modules, Section 7 discusses some additional changes to support
the timer operation, and APPENDIX A gives the details of additions to the DSP96002
instruction set.
1 SUMMARY OF NEW DSP96002 FEATURES
Instruction Cache
The functionality of the 1K internal Program Memory (PRAM) has been extended by al-
lowing it to operate as a 4K byte (1K word) "real-time" Instruction Cache. The term "real-
time" emphasizes the high degree of controllability available within the Instruction Cache
permitting deterministic results. After reset the cache is disabled and the Program Mem-
ory functionality is identical to the DSP96002 described in the DSP96002 User's Manual.
This document contains information on a new product. Specifications and information herein are subject to change without notice.
MOTOROLA INC., 1993
Order this document by
DSP96002UMAD/AD
DSP96002
MOTOROLA
May, 1993
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