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ORI
OR Immediate to Control Register
Operation:
D v #xx
D
Description:
Logically OR the contents of the control register with an 8-bit immediate operand. The result is stored back
into the specified control register. See Section A.10 for restrictions.
CCR Condition Codes:
For CCR operand:
C
- Set if bit 0 of the immediate operand is set. Not affected otherwise.
V
- Set if bit 1 of the immediate operand is set. Not affected otherwise.
Z
- Set if bit 2 of the immediate operand is set. Not affected otherwise.
N
- Set if bit 3 of the immediate operand is set. Not affected otherwise.
I
- Set if bit 4 of the immediate operand is set. Not affected otherwise.
LR
- Set if bit 5 of the immediate operand is set. Not affected otherwise.
–
R
- Set if bit 6 of the immediate operand is set. Not affected otherwise.
A
- Set if bit 7 of the immediate operand is set. Not affected otherwise.
For OMR, MR, IER, ER operands:
C
- Not affected.
V
- Not affected.
Z
- Not affected.
N
- Not affected.
I
- Not affected.
LR
- Not affected.
–
R
- Not affected.
A
- Not affected.
ER Status Bits:
For ER operand:
INX
-Set if bit 0 of the immediate operand is set. Not affected otherwise.
DZ
-Set if bit 1 of the immediate operand is set. Not affected otherwise.
UNF
-Set if bit 2 of the immediate operand is set. Not affected otherwise.
OVF
-Set if bit 3 of the immediate operand is set. Not affected otherwise.
OPERR-Set if bit 4 of the immediate operand is set. Not affected otherwise.
SNAN -Set if bit 5 of the immediate operand is set. Not affected otherwise.
NAN
-Set if bit 6 of the immediate operand is set. Not affected otherwise.
UNCC -Set if bit 7 of the immediate operand is set. Not affected otherwise.
MOTOROLA
Assembler Syntax:
OR(I)
DSP96002 USER'S MANUAL
#Mask,D
ORI
A - 287
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