Motorola DSP96002 User Manual page 22

32-bit digital signal processor
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ZZ = ^end_of_sequence
ZW = ^ext_acc_req & ^
WX = ^ext_acc_req &
WY =
NON-EXISTENT ARC
WZ =
ext_acc_req
WW = ^ext_acc_req & ^
Notes: 1. Illegal arcs in DSP96002 since once the request of the bus is pending, it will not be canceled
before the execution of the access.
2. Non-existent arc since if ext_acc_req arrives together with the negation of
becomes active master and begins its bus transfers.
3.
D
B
G is
ext_acc_req signal when it is asserted at the same phase together with
5.16.3 Bus Arbitration Example Cases
5.16.3.1 Case 1 – Normal
If the device requesting mastership asserts
B
B is deasserted indicating the bus is not busy. The requesting device will assert
5.16.3.2 Case 2 – Bus Busy
If the device requesting mastership asserts
es'
B
G; however, the bus is busy because
B
A until
B
B is deasserted.
5.16.3.3 Case 3 – Low Priority
If the device requesting mastership asserts
B
G because a higher priority device requested the bus.
serted.
5.16.3.4 Case 4 – Default
If a device does not request the bus and it is not in the bus parking state but rather it is in the idle state: the
arbiter, by design (i. e., default), asserts
MOTOROLA
v ( ext_acc_req & ^
B
G
B
G
B
G
B
G delayed by one phase. This is done to provide a response to the
B
R: the arbiter asserts the requesting devices'
B
R: the arbiter responds by asserting the requesting devic-
B
B
R: the arbiter withholds asserting the requesting devices'
B
G.
DSP96002 USER'S MANUAL
D
B
G )
(note 3)
(note 2)
B is asserted. The requesting device will not assert
B
A of the requesting device will not be as-
B
A will remain deasserted.
B
G, the device
B
G negation.
B
G and
B
A.
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