Motorola DSP96002 User Manual page 234

BRSET
Operation:
If S{n} = 1, then PC + xxxx
else PC + 1
If S{n} = 1, then PC + xxxx
else PC + 1
If S{n} = 1, then PC + xxxx
else PC + 1
If S{n} = 1, then PC + xxxx
else PC + 1
If S{n} = 1, then PC + xxxx
else PC + 1
If S{n} = 1, then PC + xxxx
else PC + 1
If S{n} = 1, then PC + xxxx
else PC + 1
Description:
The nth bit in the source operand is tested. If the tested bit is set, program execution continues at location
PC+displacement. The PC contains the address of the next instruction. If the tested bit is cleared, the PC
is incremented and program execution continues sequentially. However, the address register specified in
the effective address field is always updated independently of the condition. The displacement is a 2's
complement 32-bit integer that represents the relative distance from the current PC to the destination PC.
The 32-bit displacement is contained in the extension word of the instruction. All memory alterable ad-
dressing modes may be used to reference the source operand. Absolute Short, I/O Short and Register
Direct addressing modes may also be used. Note that if the specified source operand S is the SSH, the
stack pointer register will be decremented by one. The bit to be tested is selected by an immediate bit
number 0-31. See Section A.10 for restrictions.
CCR Condition Codes: Not affected.
ER Status Bits: Not affected.
IER Flags: Not affected.
A - 46
Branch if Bit Set
Assembler Syntax:
PC BRSET
PC
PC
BRSET
PC
PC
BRSET
PC
PC
BRSET
PC
PC
BRSET
PC
PC
BRSET
PC
PC
BRSET
PC
DSP96002 USER'S MANUAL
#bit,X: ea, label
#bit,X: aa, label
#bit,X: pp, label
#bit,Y: ea, label
#bit,Y: aa, label
#bit,Y: pp, label
#bit,S,label
BRSET
MOTOROLA