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31
31
30
29
*
DE
DIE
23
22
21
*
*
DCP
15
14
13
M7
M6
M5
7
6
5
*
*
DSS2
Figure 21 - DMA Controller Programming Model - Channel 1
7.1
DCS Reserved Bits (Bits 6, 7, 17-22, 27, 29)
These bits read as zero and should be written with zero for future compatibility.
7.2
DCS DMA Request Masks (M0-M8) Bits 8-16
The DMA Request mask bits select the source of DMA requests used to trigger DMA
transfers. If a mask bit is set, the corresponding device is selected as the DMA request
source. If the mask bit is cleared, the device is ignored. The DMA request sources may
be the internal peripherals or external devices requesting service through the IRQA,
IRQB and IRQC pins. The external inputs behave as edge-triggered synchronous inputs.
The mask bits are cleared by hardware and software reset. The internal DMA request
sources are produced by ANDing the internal peripheral status bits with DE.
48
DMA Source Modifier Register
0
DSM1
addr X:$FFFFFFD7
DMA Source Address Register
DSR1
addr X:$FFFFFFD6
DMA Source Offset Register
DSN1
addr X:$FFFFFFD5
DMA Destination Modifier Register
DDM1
addr X:$FFFFFFD3
DMA Destination Address Register
DDR1
addr X:$FFFFFFD2
DMA Destination Offset Register
DDN1
addr X:$FFFFFFD1
DMA Counter
DCO1
addr X:$FFFFFFD4
28
27
26
25
*
DTD
DTM1 DTM0 DMAP
20
19
18
17
*
*
*
12
11
10
9
M4
M3
M2
M1
4
3
2
1
DSS1 DSS0 DDS2 DDS1
24
DMA Control/Status Register
DCS1
addr X:$FFFFFFD0
16
*
M8
8
M0
0
DDS0
MOTOROLA
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