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$FFFFFFFF
$FFFFFFFE
$FFFFFFFD
$FFFFFFFC
$FFFFFFF0
$FFFFFFEF
$FFFFFFEE
$FFFFFFED
$FFFFFFEC
$FFFFFFE7
$FFFFFFE6
$FFFFFFE5
$FFFFFFE4
$FFFFFFE0
$FFFFFFDF
$FFFFFFDE
$FFFFFFDD
$FFFFFFDC
$FFFFFFDB
$FFFFFFDA
$FFFFFFD9
$FFFFFFD8
$FFFFFFD7
$FFFFFFD6
$FFFFFFD5
$FFFFFFD4
$FFFFFFD3
$FFFFFFD2
$FFFFFFD1
$FFFFFFD0
$FFFFFFCF
$FFFFFF80
MOTOROLA
X DATA Memory Space
IPR - Interrupt Priority Register
BCRA - Port A Bus Control Register
BCRB - Port B Bus Control Register
PSR
- Port Select Register
:
RESERVED
Reserved for OnCE Operation (OGDBR)
HTXA/HRXA - HOSTA HTX/HRX Register
HTXCA
- HOSTA HTX Reg. and HMRC Clear
HSRA - HOSTA Status Register
HCRA - HOSTA Control Register
:
RESERVED
HTXB/HRXB - HOSTB HTX/HRX Register
HTXCB
- HOSTB HTX Reg. and HMRC Clear
HSRB - HOSTB Status Register
HCRB - HOSTB Control Register
:
RESERVED
RESERVED
DSM0 -DMA CH0 Source Modifier Register
DSR0 -DMA CH0 Source Address Register
DSN0 -DMA CH0 Source Offset Register
DCO0 -DMA CH0 Counter Register
DDM0 -DMA CH0 Destination Modifier Register
DDR0 -DMA CH0 Destination Address Register
DDN0 -DMA CH0 Destination Offset Register
DCS0 -DMA CH0 Control/Status Register
DSM1 -DMA CH1 Source Modifier Register
DSR1 -DMA CH1 Source Address Register
DSN1 -DMA CH1 Source Offset Register
DCO1 -DMA CH1 Counter Register
DDM1 -DMA CH1 Destination Modifier Register
DDR1 -DMA CH1 Destination Address Register
DDN1 -DMA CH1 Destination Offset Register
DCS1 -DMA CH1 Control/Status Register
RESERVED
:
RESERVED
RESERVED
Figure 7-27. Internal I/O Memory Map
DSP96002 USER'S MANUAL
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