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Register
Register
Name
Contents
HCR
HYWE
HYRE
HXWE
HXRE
HPWE
HPRE
HRES
HF3-HF2
HCIE
HTIE
HRIE
HSR
HYWP
HYRP
HXWP
HXRP
HPWP
HPRP
HDMA
HF1-HF0
HCP
HTDE
HRDF
7.4.4 HI Programming Model
The HI block diagram is shown in Figure 7-9. The HI has two programming models - one for the DSP96002
programmer and one for the external host processor programmer. In most cases, the notation used reflects
the DSP96002 perspective. The HI - DSP96002 Programming Model is shown in Figure 7-10. The HI - Ex-
ternal Host Processor Programming Model is shown in Figure 7-11. The HI Interrupt Structure is shown in
Figure 7-13. The DSP96002 has two HIs. The registers of the two HIs are identical except for the addresses.
Their names have an A or B suffix identifying the port they are connected to.
7.4.5 Host Transmit Data Register (HTX) - DSP96002 Side
The Host Transmit register (HTX) is used for DSP96002 to host processor data transfers. The HTX register
is viewed as a 32-bit write-only register by the DSP96002. Writing the HTX register clears HTDE. The
DSP96002 may program the HTIE bit to cause a Host Transmit Data interrupt when HTDE is set. The HTX
register is transferred as 32-bit data to the Receive Register RX if both the HTDE bit and the Receive Data
Full RXDF status bit are cleared. This transfer operation sets RXDF and HTDE.
7 - 14
HW/SW
HOST
Reset
Reset
0
-
0
-
0
-
0
-
0
-
0
-
1
1
0
-
0
-
0
-
0
-
0
0
0
0
0
0
0
0
0
0
0
0
0
-
0
-
0
-
1
1
0
0
Figure 7-8. Host Interface Reset - DSP96002 Side
DSP96002 USER'S MANUAL
INIT
INIT
TREQ=1
TREQ=0
RREQ=0
RREQ=1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0
-
0
-
0
-
0
-
0
-
0
-
-
-
-
-
-
-
-
1
0
-
INIT
Comments
TREQ=1
RREQ=1
-
-
-
-
-
-
-
-
-
-
-
0
0
0
0
0
0
-
-
-
1
0
MOTOROLA
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