Motorola DSP96002 User Manual page 143

Int ctl cyc1 i
Int ctl cyc2
Fetch n3
Decode n2
Execute n1
i = interrupt
ii = interrupt instruction word
n = normal single word instruction
* subsequent interrupts are enabled at this time
The following one-word instructions are aborted when they are fetched in the cycle preceding the fetch of
the first interrupt instruction word (n4 or n8 in Figure 8-1): Bcc, BRA, BScc, BSR, FBcc, FBScc, FJcc,
FJScc, Jcc, JMP, JScc, JSR, LRA, REP, RESET, RTI, RTR, RTS, STOP, and WAIT.
Two-word instructions are aborted when the first interrupt instruction word fetched will replace the fetch of
the second word of the two word instruction (n5 in Figure 8-2).
Aborted instructions are re-fetched again when program control returns from the interrupt routine. The PC
is adjusted appropriately prior to the end of the decode cycle of the aborted instruction.
If the first interrupt word fetch occurs in the cycle following the fetch of a one-word instruction not listed
above or the second word of a two-word instruction, that instruction will complete normally prior to the start
of the interrupt routine.
The following cases have been identified where service of an interrupt might encounter an extra delay:
If a long interrupt routine is used to service a (F)TRAPcc interrupt, then the processor priority
1.
level is set to 3. Thus, all interrupts except for illegal instruction and stack error are disabled
until the (F)TRAPcc service routine terminates with an RTI (unless the (F)TRAPcc service
routine software lowers the processor priority level).
While servicing an interrupt the next interrupt service will be delayed according to the following
2.
rule:
After the first interrupt instruction word reaches the instruction decoder, at least four more in-
structions will be decoded before decoding the next first interrupt instruction word (see Figure
8-1). If any one pair of instructions being counted is the REP instruction followed by a instruc-
tion to be repeated then the whole "package" is counted as two instructions independently of
the number of repeats done.
3. The following instructions are uninterruptable: ILLEGAL, (F)TRAPcc, STOP, WAIT and RE-
SET.
The REP instruction and the instruction being repeated are uninterruptable.
4.
8.3.1 Interrupt Instruction Fetch
During an interrupt instruction fetch, instruction words are fetched from the interrupt starting address and
interrupt starting address+1 locations.
The interrupt controller generates an interrupt instruction fetch address which points to the first instruction
word of a two-word fast interrupt routine. This address is used for the next instruction fetch, instead of the
PC, and the interrupt instruction fetch address+1 is used for the subsequent instruction fetch. While the
MOTOROLA
i
n4 ii1 ii2 n5
n3 n4 ii1 ii2
n2 n3 n4 ii1
Figure 8-1. Interrupt Pipeline Operation
DSP96002 USER'S MANUAL
*
i
i
n6 n7 n8 ii3
n5 n6 n7 n8
ii2 n5 n6 n7
ii4
ii3 ii4
n8 ii3
8 - 3