Motorola DSP96002 User Manual page 127

_LOOP1 JCLR
MOVE
_LOOP2 JCLR
MOVE
The minimal memory write is 6 program words and 16 clock cycles. The second move triggers the X Mem-
ory Write interrupt request in the slave. The interrupt service routine in the slave takes 10-14 clock cycles
to execute. If there are other interrupts with higher priority the response to this interrupt may be delayed.
A somewhat faster procedure may be employed by ensuring that sufficient time has elapsed after the writing
the address to TX before writing the data to eliminate testing for TXDE=1 as above:
_LOOP JCLR
MOVE
NOP
MOVE
This procedure requires 5 program words and 12 clock cycles. The NOP instruction provides the necessary
elapse time between two consecutive TX writes if both master and slave processors are being fed the same
clock frequency and duty cycle, otherwise a second NOP instruction should be added to the above code.
7.4.21.10 X/Y/P Memory Read Procedure
The X/Y/P Memory Read procedure enables the host processor to read a data word D from an arbitrary
address A located in the DSP96002 memory space. The host processor must execute the following steps:
Verify that TX is empty (TXDE=1).
1.
Write A into the TX register using the host function "TX register write and X/Y/P Memory Read
2.
Interrupt". This sets HMRC. If HRX is empty, the HI then transfers A to HRX automatically and
initiates the X/Y/P Memory Read interrupt.
In the DSP96002 side, the X/Y/P Memory Read interrupt vector should point to a routine that
3.
first reads HRX to get the address A, stores A in an address pointer Rn, reads the memory
location pointed to by Rn, and stores the data D in the HTX register using the HTXC address.
The data D passes to the RX register (host processor side), HMRC is cleared and RXDF is set
(this may assert
MOTOROLA
#TXDE,X:(R4),_LOOP1
R1,X:(R3)
#TXDE,X:(R4),_LOOP2
R0,X:(R3)
#TRDY,X:(R4),_LOOP
R1,X:(R3)
R0,X:(R3)
— –
H R).
DSP96002 USER'S MANUAL
clock
words cycles
2
1
2
1
6
clock
words cycles
2
1
1
1
5
6
2
6
2
16
6
2
2
2
12
7 - 41