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95 94
74 73 72 71
S
†
† † †
Notes: * –
i = 1 when normalized
i = 0 when unnormalized
† – When NaN, bits 71, 72, 73 = 1
When not NaN Bit 74
Bits 73, 72, 71 are complement
of Bit 74.
(1) – Bits 32-39 are nonzero when the register
contains a SEP floating point result or a
DP floating point number.
Bits 32-39 are zero when the register
contains a SP floating point number.
Figure C-10a. Automatic Format Conversion – Single Precision
The registers d8 and d9 are auxiliary registers which can be used for temporary data storage. Their main
purpose is to allow a fast, four-cycle radix-2, decimation in time FFT butterfly kernel, though their use is cer-
tainly not limited to this application. d8 and d9 can be used as source operands in multiply operations and
MOVE instructions, but can only be written as destinations of MOVE instructions.
The format conversion unit provides automatic format conversion from/to the SP and DP memory storage
formats to/from the DP storage format in the data ALUs register file. The conversion is depicted in Figure
C-10 and is done in a transparent fashion.
When moving SP numbers into the data ALU (see Figure C-10a), the 52-bit fraction of the DP internal for-
mat is written with the 23-bit fraction of the source in its most significant bits, and the implicit integer bit is
made explicit. The remaining bits of the fraction are set equal to zero. If the number in question is denor-
malized (exponent = e
min
zero" mode (indicated by the FZ bit in the Status Register), the number is considered zero when used as
an operand for floating-point operations, although the contents of the register are not changed. In the IEEE
MOTOROLA
31 30 29
S
e
64
63 62
*
e
Fraction
i
31 30 29
S
e
Bit 30
and the first bit of the mantissa = 0), the U tag is set. In the non-IEEE "flush to
DSP96002 USER'S MANUAL
23 22
0
Fraction
40 39
32 31
(1)
23 22
0
Fraction
(2) – Bits 11-31 are only nonzero when the
register contains a DP floating point
number.
(3) – Bits 0-10 are always zero when
representing a floating point number.
X or Y Data Memory
11 10
0
(3)
(2)
X or Y Data Memory
C-11
Dn
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