Motorola DSP96002 User Manual page 23

5.16.3.5 Case 5 – Bus Lock during RMW
If the device requesting mastership asserts
— –
and B B is deasserted, then the requesting device will assert
struction which accesses external memory is being executed, and the bus arbiter deasserts
— –
B A will remain asserted until the entire RMW instruction completes execution.
serted thereby relinquishing the bus. Note that during external RMW instruction execution,
—
ed. In general, the B
master at a time. That is, referring to Figure 2-10,
— –
which prevents T A from being asserted by the controller (thereby suspending the memory access by
DSP #2) until DSP #1 completes its RMW access.
DSP96002
#1
RMW
5.16.3.6 Case 6 – Bus Park
The device requesting mastership asserts
— –
B B is deasserted indicating the bus is not busy – the requesting device will assert
requesting device no longer requires the bus it will deassert
ed because other requests are not pending, then
parking and eliminates the need for the last bus master to rearbitrate for the bus during its next external
access.
2 - 20
—
–
L signal can be used to ensure that a multiport memory can only be written by one
— –
B L
Figure 2-10. Bus Lock During RMW
—
B
DSP96002 USER'S MANUAL
–
B R and the arbiter asserts the requesting devices'
— –
B
— –
B L can be input from DSP #1to the memory controller
Dual Port
Memory
Controller
—
–
R; the arbiter asserts the requesting devices'
— –
B R; if the bus arbiter leaves
— –
B A will remain asserted. This condition is called bus
A. If a read-modify-write (RMW) in-
—
— –
B A will then be deas-
— –
B
DSP96002
#2
–
T A
— –
B A. When the
—
B
MOTOROLA
— –
B G
–
B G, then
L is assert-
— –
B G and
–
G assert-