Motorola DSP96002 User Manual page 14

(BSET, BCLR, BCHG) will not give up bus mastership until the end of the current instruc-
tion.
— –
B A (Bus Acknowledge) - Open drain, active low output. When deasserting
DSP96002 drives
up. In this way, only a weak external pull-up resistor is required to hold the line high.
–
B A may be directly connected to
MC68040
bus master. It waits until
the previous bus master is off the bus. The pending bus master asserts
come the current bus master.
bus and is the bus master. While
bus (the bus master). When
may be used as a three-state enable control for external address, data and bus control
signal buffers.
Note that a current bus master may keep
gardless of whether
allows the current bus master to use the bus repeatedly without re-arbitration until some
other device wants the bus.
The current bus master keeps
cycles, regardless of whether
tion unit. This form of "bus locking" allows the current bus master to perform atomic op-
erations on shared variables in multitasking and multiprocessor systems. Current in-
structions which perform indivisible read-modify-write bus cycles are BCLR, BCHG and
BSET.
— –
B B (Bus Busy) - active low input, must be asserted and deasserted synchronous to the input
clock (CLK) for proper operation.
the external bus. In multiple DSP96002 systems, all
are driven by the logical AND of all
master (directly or indirectly by
master.
negation) to indicate that it is off the bus and is no longer the bus master. The pending
bus master monitors the
ter asserts
indirectly.
MOTOROLA
—— –
B G is ignored during hardware reset.
— –
B A high during half a CLK cycle and then disables the active pull-
— –
B B pin. When
—
B
— –
B A is three-stated during hardware reset.
— –
B R is asserted or deasserted. This is called "bus parking" and
— –
B B is deasserted by the current bus master (directly or indirectly by
— –
B
— –
B A to become the current bus master, which asserts
DSP96002 USER'S MANUAL
— –
B B in order to obtain the same functionality as the
— –
B G is asserted, the DSP96002 becomes the pending
–
B is negated by the previous bus master, indicating that
— –
B A is asserted when the CPU or DMA has taken the
— –
B A is asserted, the DSP96002 is the owner of the
— –
B A is negated, the DSP96002 is a bus slave.
— –
B A asserted after ceasing bus activity, re-
— –
B A asserted during indivisible read-modify-write bus
— –
B G has been deasserted by the external bus arbitra-
— –
B B is deasserted when there is no bus master on
—
— – —
B A outputs.
— –
B A assertion) to indicate that it is now the current bus
B signal until it is deasserted. Then the pending bus mas-
—
—
B
–
B B inputs are tied together and
–
B B is asserted by a pending bus
— –
B B directly or
–
B A, the
—
–
A to be-
— –
B A
— –
B A
2 - 11