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6.1
INTRODUCTION
This chapter introduces the DSP96002 instruction set and instruction format. The complete range of in-
struction capabilities combined with the flexible addressing modes described in Chapter 5 provide a very
powerful assembly language for digital signal processing and graphics algorithms. The instruction set has
been designed to allow efficient coding for high-level language compilers and yet be easily programmed in
assembly language.
As indicated by the programming model in Chapter 4, the DSP96002 architecture can be viewed as three
execution units operating in parallel (Data ALU, Address Generation Unit and Program Controller). The
goal of the instruction set is to keep each of these units busy during each instruction cycle. This achieves
maximum throughput and minimum use of program memory.
6.2
INSTRUCTION GROUPS
The instruction set is divided into the following groups:
•
Floating-Point Arithmetic
•
Fixed-Point Arithmetic
•
Logical
•
Bit Manipulation
•
Loop
•
Move
•
Program Control
Each instruction group is described in the following sections. Detailed information on each of the 133 in-
structions is given in Appendix A.
6.2.1 Floating-Point Arithmetic Instructions
All floating-point arithmetic instructions operate on the 96-bit Data ALU registers. The floating-point arith-
metic instructions are register-based (register direct addressing modes used for operands) and execute
within the Data ALU. This means that the X Data Bus, Y Data Bus and the Global Data Bus are free for
optional parallel move operations. This allows new data to be pre-fetched for use in following instructions
and results calculated by previous instructions to be stored. Floating-point instructions always execute in
a single instruction cycle in the Flush-to-Zero mode. Floating-point instructions execute in a single instruc-
MOTOROLA
SECTION 6
INSTRUCTION SET AND EXECUTION
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DSP96002 USER'S MANUAL
6 - 1
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