Motorola DSP96002 User Manual page 409

32-bit digital signal processor
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LSR
Operation:
31
0
Assembler Syntax:
LSR
D
(move syntax - see the Move instruction description.)
LSR
S,D
(move syntax - see the Move instruction description.)
LSR
#shift,D
Description:
Single-bit shift:
Logically shift the low portion of the specified operand one bit to the right. The carry bit receives the LSB
shifted out of the low portion of the source operand. A zero is shifted into bit 31 of the operand. The result
is stored in the low portion of D.
Multi-bit shift:
Logically shift the low portion of the specified operand N bits (up to 63 bits) to the right. The number of bits
to shift is determined by the 11-bit unsigned integer located in the 11 LSBs of the high portion of S or by a
6-bit immediate field in the instruction. The carry bit receives the Nth bit shifted out of the low portion of
the source operand; it is cleared for a shift count of zero. N zeros are shifted into the MSBs of the desti-
nation operand. If more than 32 bits are shifted, zeros will be stored in D and the carry bit. The result is
stored in the low portion of D.
Input Operand(s) Precision: 32-bit integer.
Output Operand Precision: 32-bit integer.
CCR Condition Codes:
C
V
Z
N
I
LR
R
A
ER Status Bits: Not affected.
IER Flags: Not affected.
MOTOROLA
Logical Shift Right
0
- Set if the last bit shifted out of the operand is set. Cleared otherwise. Cleared for a
shift count of zero.
- Always cleared.
- Set if result is zero. Cleared otherwise.
- Set if result is negative. Cleared otherwise.
- Not affected.
- Not affected.
- Not affected.
- Not affected.
DSP96002 USER'S MANUAL
C
(parallel data bus move)
LSR
A - 221

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