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AND
Operation:
D.L & S.L
D.L
Description:
Logically AND the low portion of the two specified operands and store the result in the low portion of D.
Input Operand(s) Precision: 32-bit integer.
Output Operand Precision: 32-bit integer.
CCR Condition Codes:
C
- Not affected.
V
- Always cleared.
Z
- Set if result is zero. Cleared otherwise.
N
- Set if result is negative. Cleared otherwise.
I
- Not affected.
LR - Not affected.
–
R - Not affected.
A
- Not affected.
ER Status Bits:
Not affected.
IER Flags:
Not affected.
Instruction Format: AND
Instruction Fields:
31
DATA BUS MOVE FIELD
OPTIONAL EFFECTIVE ADDRESS EXTENSION OR IMMEDIATE LONG DATA
D
Dn.L
S
Dn.L
Timing: 2 + mv oscillator clock cycles
Memory: 1 + mv program words
A - 22
Logical AND
(parallel data bus move)
S,D
(move syntax - see the MOVE instruction description.)
(u u)
d d d
n n n
where nnn = 0-7
s s s
n n n
where nnn = 0-7
DSP96002 USER'S MANUAL
Assembler Syntax:
AND
S,D
(move syntax - see the MOVE instruc-
tion description.)
14 13
00
0sss
AND
0
uu00
1ddd
MOTOROLA
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