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DSP96002 Bus Master
DMA Source
DMA Request
Bus Master
Write Bus Cycle
from Memory
Figure 7-17. DSP96002 to DSP96002 Data Write
sors are used to transfer data without interfering with the local processing in both chips. Figure 7-17 contains
a diagram showing the data paths and control lines used for the data transfers.
A data write transfer is initiated when the slave's
is empty and ready to receive a data word from the master. The
pin in the master where this pin is defined as a DMA service request input. When
master DMA Controller transfers the data word from the master's memory to an external address selecting
the TX register in the slave's HI as destination. After TX is written (negating
by the HI to the HRX register, setting HRDF and TXDE. Setting TXDE causes
is set. In the slave's DMA Controller, HRDF is defined as a DMA service request signal. When HRDF is
asserted, the slave's DMA Controller initiates a data transfer from HRX to the slave memory, completing the
data transfer.
7.4.19.2
Data Read Using The On-Chip DMA Controllers
This example outlines the steps that a DSP96002 bus master, behaving as host processor, transfers data
from a DSP96002 bus slave, thorough the slave's HI. The on-chip DMA Controllers of both DSP96002 pro-
cessors are used to transfer data without interfering with the local processing in both chips. Figure 7-18 con-
tains a diagram showing the data paths and control lines used for the data transfers.
A data read transfer is initiated when the slave's
is full and the data is ready to be read by the master.
MOTOROLA
—
—
–
I
R
Q
space
slave
S1, S0
select
address
A0–A31
decode
—
–
T
A
—
–
T
S
—
R/
W
data
DSP96002 USER'S MANUAL
empty
V
cc
—
–
H
R signal is asserted, indicating that its HI TX register
—
–
H
R signal is connected to an
—
–
H
R signal is asserted, indicating that its HI RX register
—
–
H
R is connected to an
DSP96002 Bus Slave
DMA Destination
—
–
DMA Request
H
R
—
–
Host
Memory
H
S
DMA Transfer
—
–
Transmit Data
H
A
Empty (TXDE=1)
A2–A5
—
–
T
S
—
R/
W
D0–D31
Host Data Full
(HRDF=1)
–
—
–
H
R is asserted, the
—
–
H
R), the data is transferred
—
–
H
R to be asserted if TREQ
–
—
–
I
R
Q pin in the master
—
–
I
R
Q
7 - 33
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