Logic Unit - Motorola DSP96002 User Manual

Linkages are provided to shift in/out the condition code carry (C) bit.
3.3.2.4 Exponent Comparator and Update Unit
EXC is an 11-bit subtracter which compares the exponents of the two operands of the add/subtract opera-
tions. It receives its inputs on the AEIA and AEIB buses from the high portion of the registers and delivers
as result the largest exponent and the difference between the exponents. The exponent difference is de-
livered to the barrel shifter which uses this information for the mantissa alignment process required by the
floating point add/subtract operations. The largest exponent is delivered to exponent update units which
may update it according to the result of the postnormalization process. The final result is supplied on the
AEOA and/or AEOS buses and stored in the high portion of the destination register(s).

3.3.3 Logic Unit

The logic unit in the Data ALU performs the logical operations AND, ANDC, OR, ORC, EOR, NOT, ROR
and ROL on Data ALU integer registers. It also performs the SPLIT, SPLITB, JOIN, JOINB, EXT and EXTB
field manipulation instructions. The logic unit is 32-bits wide and operates on data in the low portion of the
registers. The high and middle portions of the registers are not affected.
3.3.4 Divide and Square Root Unit
The Divide and Square Root Unit supports execution of the divide and square root operations. These op-
erations are done using iterative algorithms that require an initial seed (first approximation) of 1/x and sqr(1/
x).
3.3.5 Controller and Arbitrator
The controller and arbitrator unit (CA) supplies the control signals required by the processing units of the
Data ALU and register file and is responsible for the full implementation of the IEEE standard. For the latter
task the actions taken by the controller and arbitrator are determined by the FZ bit in the SR register. In the
"Flush-to-Zero" mode, all denormalized input operands are considered as being zero and all denormalized
results are "flushed to zero". Denormalized numbers include floating point zero. In the "IEEE" mode, all de-
normalized input operands are correctly used in calculations and denormalized results are computed and
stored correctly, according to the IEEE standard. The DSP96002 is not able to perform operations on de-
normalized numbers in a single cycle when in IEEE mode, except for operations done in the floating point
adder when the operand is a denormalized number in SEP. The controller and arbitrator unit is responsible
for generating the appropriate sequence that deals with such situations.
When detecting denormalized numbers as input operands, the controller and arbitrator unit will add one
extra cycle for entering the IEEE Mode procedure and afterwards it will add extra cycles, one for each de-
normalized input operand(s). These extra cycles are used for normalizing the input operand. After the nor-
malization, the operand is stored in a temporary format which has a negative biased exponent ("wrapped
format") but which is not available to the user. The original value of the operand in the source register is
however not affected. During the IEEE Mode procedure the activity of the chip is suspended and it is re-
sumed after all the input operands have been normalized. When detecting denormalized numbers as out-
put results, the controller and arbitrator unit will enter the IEEE Mode Procedure and will add extra cycles,
one for each denormalized output result.
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