Motorola DSP96002 User Manual page 430

Move
FFcc
Operation:
If cc, then
Opcode Operation
Description:
If the specified floating-point condition is true, transfer data from the specified source S to the specified
destination D. Also, store result(s) of the specified Data ALU operation. If the specified condition is false,
no destinations are altered. The CCR and ER registers are not updated with the condition codes gener-
ated by the Data ALU operation. The UNCC bit in the ER register and SIOP flag in the IER are set by the
FFcc instruction if the NAN bit in the ER register was set and the specified condition is one of the condi-
tions with a "Yes" entry in the "Set UNCC" column. If no register move is specified, this instruction is as-
sembled with a R0 to R0 move.
"cc" may specify the following conditions:
Mnemonic
EQ - equal
ERR - error
GE - greater than or equal
GL - greater or less than
GLE - greater, less or equal
GT - greater than
INF - infinity
LE - less than or equal
LT - less than
MI - minus
NE(Q) - not equal
NGE - not(greater than or equal)
NGL - not(greater or less than)
NGLE - not(greater, less or equal)
NGT - not greater than
NINF - not infinity
NLE - not(less than or equal)
NLT - not less than
OR - ordered
PL - plus
UN - unordered
Note: The operands for the ERR condition are taken from the ER register.
* See description of UNcc bit in Section A.4.
A - 242
Floating-Point iF
Conditional Instruction
without CCR, ER, IER update
S D
DSP96002 USER'S MANUAL
Assembler Syntax:
Opcode-Operands
Opcode-Operands
Condition
Z = 1
UNCC v SNAN v OPERR v No
OVF v UNF v DZ = 1
NAN v (N & ~Z) = 0
NAN v Z = 0
NAN = 0
NAN v Z v N = 0
I = 1
NAN v ~(N v Z) = 0
NAN v Z v ~N = 0
N = 1
Z = 0
NAN v (N & ~Z) = 1
NAN v Z = 1
NAN = 1
NAN v Z v N = 1
I = 0
NAN v ~(N v Z) = 1
NAN v Z v ~N = 1
NAN = 0
N = 0
NAN = 1
Move
FFcc
S,D FFcc
FFcc
Non-aware
Set UNCC*
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
MOTOROLA