Motorola DSP96002 User Manual page 286

FBcc Floating-Point Branch Conditionally
Operation:
If cc, then PC+xx
else PC+1
If cc, then PC+xxxx
else PC+1
If cc, then PC+Rn
else PC+1
Description:
If the specified floating-point condition is true, the address of the instruction immediately following the FB-
Scc instruction and the status register are pushed onto the stack. Program execution then continues at
location PC+displacement. The PC contains the address of the next instruction. If the specified condition
is false, the PC is incremented and program execution continues sequentially. The displacement is a 2's
complement 32-bit integer that represents the relative distance from the current PC to the destination PC.
Short Displacement, Long Displacement and Address Register PC Relative addressing modes may be
used. The Short Displacement 15-bit data is sign extended to form the PC relative displacement. See
Section A.10 for restrictions. Non-aware floating-point conditions set the SIOP flag in the IER register and
the UNCC bit in the ER register if the NAN bit is set.
"cc" may specify the following conditions:
Mnemonic
EQ
ERR
GE
GL
GLE
GT
INF
LE
LT
MI
NE(Q) - not equal
NGE
NGL
NGLE - not(greater, less or equal) NAN = 1
NGT
NINF - not infinity
NLE
NLT
OR
PL
UN
Note: The operands for the ERR condition are taken from the ER register.
See the description of UNcc in Section A.4.
CCR Condition Codes: Not affected.
A - 98
PC
PC
PC
PC
PC
PC
- equal
- error
- greater than or equal
- greater or less than
- greater, less or equal
- greater than
- infinity
- less than or equal
- less than
- minus
- not(greater than or equal) NAN v (N & ~Z) = 1
- not(greater or less than)
- not greater than
- not(less than or equal)
- not less than
- ordered
- plus
- unordered
DSP96002 USER'S MANUAL
Assembler Syntax:
FBcc label (short)
FBcc label
FBcc Rn
Condition
Z = 1
UNCC v SNAN v OPERR v No
OVF v UNF v DZ = 1
NAN v (N & ~Z) = 0
NAN v Z = 0
NAN = 0
NAN v Z v N = 0
I = 1
NAN v ~(N v Z) = 0
NAN v Z v ~N = 0
N = 1
Z = 0
NAN v Z = 1
NAN v Z v N = 1
I = 0
NAN v ~(N v Z) = 1
NAN v Z v ~N = 1
NAN = 0
N = 0
NAN = 1
FBcc
Non-aware
Set UNCC*
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
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