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BSET
Operation:
D{n}
C;
1
D{n}
D{n}
C;
1
D{n}
D{n}
C;
1
D{n}
D{n}
C;
1
D{n}
D{n}
C;
1
D{n}
D{n}
C;
1
D{n}
D{n}
C;
1
D{n}
Description:
The nth bit of the destination operand is tested and the state of the nth bit is reflected in the C condition
code bit. After the test, the nth bit is set in the destination. All memory alterable addressing modes may
be used. Register, Absolute Short and I/O Short addressing may also be used.
The bit to be tested is selected by an immediate bit number 0-31. This instruction performs a read-modify-
write operation on the destination operand and requires two destination accesses. This instruction pro-
vides a test-and-set capability which is useful for synchronizing multiple processors using a shared mem-
ory. See Section A.10 for restrictions.
CCR Condition Codes:
For destination operand SR:
C
V
Z
N
I
LR
–
R
A
A - 54
Bit Test and Set
- Set if bit 0 is specified. Not affected otherwise.
- Set if bit 1 is specified. Not affected otherwise.
- Set if bit 2 is specified. Not affected otherwise.
- Set if bit 3 is specified. Not affected otherwise.
- Set if bit 4 is specified. Not affected otherwise.
- Set if bit 5 is specified. Not affected otherwise.
- Set if bit 6 is specified. Not affected otherwise.
- Set if bit 7 is specified. Not affected otherwise.
DSP96002 USER'S MANUAL
Assembler Syntax:
BSET
#bit,X: ea
BSET
#bit,X: aa
BSET
#bit,X: pp
BSET
#bit,Y: ea
BSET
#bit,Y: aa
BSET
#bit,Y: pp
BSET
#bit,D
BSET
MOTOROLA
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