Motorola DSP96002 User Manual page 116

busy semaphore bit), several bits or write the whole 16 bits (which, for example, may be used as host pro-
cessor ID).
Host processors should use read/modify/write uninterruptable instructions (such as XMEM in the
MC88000, CAS in the MC680x0, or BSET in the DSP96002) and examine which host processor has allo-
cated the HI or set the semaphore bit by "bit test and set" instructions. The BSET in the DSP96002 is "un-
interruptable" in that it tests the semaphore bit and indicates the results in the status register and then sets
the semaphore bit without relinquishing the bus. This combined operation prevents another processor from
reading or writing the semaphore bit between the BSET testing and setting operations.
After the present HI "owner" has completed its transfers, it must release the HI (if there are other potential
masters capable of host transfers) by clearing the Semaphore Register bits. SEM0-SEM15 are cleared by
HW/SW reset.
7.4.14.2 SEM Reserved bits (Bits 16-31)
Reserved bits are read by the host processor as zeros. They should be written with zero for future compat-
ibility.
7.4.15 Interrupt Vector Register (IVR) - Host Processor Side
The Interrupt Vector Register (IVR) is a 32-bit read/write register which contains the exception vector num-
ber for use with MC680x0 processor family vectored interrupts.
7.4.15.1 IVR Interrupt Vector (IVR0-IVR7) Bits 0-7
When not in DMA Mode (DMAE=0), the contents of the IVR register may be read to the data bus by assert-
— – —
ing T S when both
during HW/SW reset. This corresponds to the un-initialized exception vector in the MC68K family.
The IVR register may also be accessed by the host processor as a regular read/write register using the ad-
dress lines A2-A5 as shown in Figure 7-12.
7.4.15.2 IVR Reserved Bits – Bits 8-31
The upper 24-bits are reserved and are read by the host processor as zeros. They should be written with
zero for future compatibility.
7.4.16 HI Interrupts
The HI may request interrupt service from either the DSP96002 core or the external host processor.
The HI interrupt requests to the DSP96002 core are internal and do not require the use of an external inter-
rupt pin. The DSP96002 core services HI interrupts by fetching the appropriate interrupt vector locations
(see Section 8). The interrupt service routine must read or write the appropriate HI register to clear the in-
terrupt request (reading HRX to clear HRDF for example). In the case of Host Command interrupts, the in-
terrupt acknowledge from the DSP96002 core, generated when the second interrupt vector location is
fetched, will clear the pending interrupt condition.
7 - 30
– — –
H R and H A are asserted. The contents of the IVR register are initialized to $0F
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