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TREQ RREQ TYEQ
0
0
0
1
1
0
1
1
x
0
x
1
Figure 7-15. HREQ and — H – R Definition - Interrupt Mode (DMAE=0)
TREQ RREQ
0
0
0
1
1
0
1
1
x
x
HREQ, — H – R and DMA Transfer Direction Definition - DMA Mode (DMAE=1)
7.4.13.9
ICS Host Flag 0 (HF0) Bit 8
The Host Flag 0 (HF0) bit is used as a general purpose flag for host processor to DSP96002 communica-
tion. HF0 may be set or cleared by the host processor. HF0 is cleared by HW/SW reset. The status of HF0
can be read in the HSR, bit 3.
7.4.13.10
ICS Host Flag 1 (HF1) Bit 9
The Host Flag 1 (HF1) bit is used as a general purpose flag for host processor to DSP96002 communica-
tion. HF1 may be set or cleared by the host processor. HF1 is cleared by HW/SW reset. The status of HF1
can be read in the HSR, bit 4.
7.4.13.11
ICS Host Flag 2 (HF2) Bit 10
The read-only Host Flag 2 (HF2) bit indicates the state of Host Flag 2 (HF2) in the Host Control Register
HCR. HF2 can only be changed by the DSP96002. HF2 is cleared by HW/SW reset.
7.4.13.12
ICS Host Flag 3 (HF3) Bit 11
The read-only Host Flag 3 (HF3) bit indicates the state of Host Flag 3 (HF3) in the Host Control Register
HCR. HF3 can only be changed by the DSP96002. HF3 is cleared by HW/SW reset.
7.4.13.13
ICS DMA Mode Enable (DMAE) Bit 12
The DMA Mode Enable bit (DMAE) selects the mode of operation of the HI. When DMAE is set, the HI op-
erates in the DMA Mode. When DMAE is cleared, the DMA Mode is disabled. Cleared by HW/SW reset.
When DMAE is cleared, the HI registers are selected by address lines A2-A5. This mode of operation is
appropriate for interfacing with external devices, such as a microprocessor, that are able to supply address-
7 - 28
HREQ flag and
0
No interrupts (polling).
0
RX full or HTX full.
0
TX empty or HRX empty.
0
RX full, HTX full, TX empty or HRX empty.
1
TX empty and HRX empty.
1
All interrupts (no polling).
TYEQ HREQ flag and
0
Reserved
0
DSP96002 DMA
0
DMAÆ DSP96002 Request (TX empty)
0
Reserved
1
Reserved
Figure 7-16.
DSP96002 USER'S MANUAL
—
–
H
R pin
—
–
H
R pin
Request (RX full)
MOTOROLA
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