Motorola DSP96002 User Manual page 278

32-bit digital signal processor
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FADD.S
Operation:
D + S
ROUND(SP)
(parallel data bus move)
Description:
Add the two specified operands, round to single precision and store the result in the destination operand D.
Input Operand(s) Precision: SEP Floating-Point.
Output Operand Precision: SP Floating-Point.
CCR Condition Codes:
C
V
Z
N
I
LR
R
A
ER Status Bits:
INX
DZ
UNF
OVF
OPERR-Set if operands are opposite-signed infinities. Cleared otherwise.
SNAN -Set if operand is a signaling NaN. Cleared otherwise.
NAN
UNCC -Always cleared.
IER Flags: Flags changed according to standard definition.
Instruction Format: FADD.S S,D
A - 90
Floating-Point Add
D
- Not affected.
- Not affected.
- Set if result is zero. Cleared otherwise.
- Set if result is negative. Cleared otherwise.
- Set if result is infinity. Cleared otherwise.
- Not affected.
- Not affected.
- Not affected.
-Set if result is inexact. Cleared otherwise.
-Always cleared.
-Set if result underflows. Cleared otherwise.
-Set if result overflows. Cleared otherwise.
-Set if result is a NaN. Cleared otherwise.
(move syntax - see the MOVE instruction description.)
DSP96002 USER'S MANUAL
Assembler Syntax:
FADD.S S,D
(move syntax - see the MOVE instruc-
tion description.)
FADD.S
MOTOROLA

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