Execution From Ram - Motorola MPC8260 PowerQUICC II User Manual

Table 13-2. Peripheral Prioritization (Continued)
Priority
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
1
The priority of each IDMA channel is programmed independently. See the
RCCR[DRxQP] description in Section 13.3.6, ÒRISC Controller ConÞguration
Register (RCCR).Ó

13.3.5 Execution from RAM

The CP has an option to execute microcode from a portion of user RAM located in the dual-
port RAM. In this mode, the CP fetches instructions from both the dual-port RAM and its
own private ROM. This mode allows Motorola to add new protocols or enhancements to
the MPC8260 in the form of RAM microcode packages. If preferred, the user can obtain
binary microcode from Motorola and load it into the dual-port RAM.
13.3.6 RISC Controller ConÞguration Register (RCCR)
The RISC controller conÞguration register (RCCR) conÞgures the CP to run microcode
from ROM or RAM and controls the CPÕs internal timer.
MOTOROLA Chapter 13. Communications Processor Module Overview
SCC2 transmit
SCC3 receive
SCC3 transmit
SCC4 receive
SCC4 transmit
IDMA[1Ð4] emulation (option 2)
SMC1 receive
SMC1 transmit
SMC2 receive
SMC2 transmit
SPI receive
SPI transmit
2
I C receive
2
I C transmit
RISC timer table
IDMA[1Ð4] emulation (option 3)
Part IV. Communications Processor Module
Request
1
1
13-7