Motorola MPC8260 PowerQUICC II User Manual page 253

bus, but some slaves or masters do not support these features. Clear BCR[ETM] to disable
this type of transaction. This places the MPC8260 in strict 60x bus mode. The following
tables are extensions to Table 8-9, Table 8-8, and Table 8-10.
Table 8-11 lists the patterns of the extended data transfer for write cycles when MPC8260
initiates an access. Note that 16- and 24-byte transfers are always eight-byte aligned and
use a 64-bit or less port size.
Table 8-11. Data Bus Contents for Extended Write Cycles
Transfer Address
Size State A[29Ð
TSIZ[0Ð3]) 31]
5 Bytes 000
(0101)
011
6 Bytes 000
(0110)
010
7 Bytes 000
(0111)
001
Table 8-12 lists the bytes required on the data bus for extended read cycles. Note that 16-
and 24-byte transfers are always 8-byte aligned and use a maximum 64-bit port size.
Table 8-12. Data Bus Requirements for Extended Read Cycles
Transfer Address
Size State
TSIZ[0Ð3] A[29-31]
0Ð7 8Ð15 16Ð23 24Ð31 32Ð39 40Ð47 48Ð55 56Ð63 0Ð7 8Ð15 16Ð23 24Ð31 0Ð7 8Ð15 0Ð7
5 Byte 000 OP0 OP1 OP2
(0101)
011 Ñ
6 Byte 000 OP0 OP1 OP2
(0110)
010 Ñ
7 Byte 000 OP0 OP1 OP2
(0111)
001 Ñ OP1 OP2
Table 8-13 includes added states to the transfer size calculation state machine. Only
extended transfers use these states.
MOTOROLA
D[0Ð7] D[8Ð15] D[16Ð23] D[24Ð31] D[32Ð39] D[40Ð47] D[48Ð55] D[56Ð63]
OP0 OP1 OP2
OP3 OP3 Ñ
OP0 OP1 OP2
OP2 OP3 OP2
OP0 OP1 OP2
OP1 OP1 OP2
Port Size/Data Bus Assignments
64-Bit
OP3 OP4
Ñ Ñ OP3 OP4 OP5
OP3 OP4 OP5
Ñ OP2 OP3 OP4 OP5
OP3 OP4 OP5
OP3 OP4 OP5
Chapter 8. The 60x Bus
Part III. The Hardware Interface
External Data Bus Pattern
OP3 OP4
OP3 OP4
OP3 OP4
OP3 OP4
OP3 OP4
OP3 OP4
Ñ Ñ Ñ OP0 OP1
OP6 OP7 Ñ
Ñ Ñ OP0 OP1
OP6 OP7 Ñ
OP6 Ñ OP0 OP1
OP6 OP7 Ñ OP1
Ñ Ñ
OP5 OP6
OP5 Ñ
OP5 OP6
OP5 OP6
OP5 OP6
32-Bit 16-Bit
OP2 OP3 OP0 OP1 OP0
Ñ Ñ OP3 Ñ
OP2 OP3 OP0 OP1 OP0
Ñ OP2 OP3 OP2 OP3 OP2
OP2 OP3 OP0 OP1 OP0
OP2 OP3 Ñ
Ñ
OP7
Ñ
OP7
Ñ
OP7
8-Bit
OP3 OP3
OP1 OP1
8-21