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Part IV. Communications Processor Module
13.3 Communications Processor (CP)
The communications processor (CP), also called the RISC microcontroller, is a 32-bit
controller for the CPM that resides on a separate bus from the core and, therefore, can
perform tasks independent of the PowerPC core. The CP handles lower-layer
communications tasks and DMA control, freeing the core to handle higher-layer activities.
The CP works with the peripheral controllers and parallel port to implement
user-programmable protocols and manage the serial DMA (SDMA) channels that transfer
data between the I/O channels and memory. It also manages the IDMA (independent DMA)
channels and contains an internal timer used to implement up to 16 additional software
timers.
The CPÕs architecture and instruction set are optimized for data communications and data
processing required by many wire-line and wireless communications standards.
13.3.1 Features
The following is a list of the CPÕs important features.
¥ One system clock cycle per instruction
¥ 32-bit instruction object code
¥ Executes code from internal ROM or RAM
¥ 32-bit ALU data path
¥ 64-bit dual-port RAM access
¥ Optimized for communications processing
¥ Performs DMA bursting of serial data from/to dual-port RAM to/from external
memory
13.3.2 CP Block Diagram
The CP contains the following functional units:
¥ Scheduler and sequencer
¥ Instruction decoder
¥ Execution unit
¥ Load/store unit (LSU)
¥ Block transfer unit (BTM)Ñmoves data between serial FIFO and RAM
¥ Eight general purpose registers (GPRs)
¥ Special registers, CRC machine, HDLC framer
The CP also gives SDMA commands to the SDMA. The CP interfaces with the dual-port
RAM for loading and storing data and for fetching instructions while running microcode
from dual-port RAM.
13-4
MPC8260 PowerQUICC II UserÕs Manual
MOTOROLA
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