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Part IV. Communications Processor Module
Table 35-8. Port D Dedicated Pin Assignment (PPARD = 1) (Continued)
Pin
PDIRD = 1 (Output)
PD20
SCC4: RTS
SCC4: TENA
Ethernet
PD19
FCC1: TxAddr[4]
MPHY, master,
multiplexed polling
FCC2: TxAddr[3]
MPHY, master,
multiplexed polling
PD18
FCC1: RxAddr[4]
MPHY, master,
multiplexed polling
FCC2: RxAddr[3]
MPHY, master,
multiplexed polling
PD17
BRG2: BRGO
PD16
FCC1: TxPrty
UTOPIA
PD15
TDM_C2: L1RQ
PD14
TDM_C2: L1CLKO
PD13
SI1: L1ST1
PD12
SI1: L1ST2
PD11
TDMB2: L1RQ
PD10
TDMB2: L1CLKO
PD9
SMC1: SMTXD
35-18
PSORD = 0
PDIRD = 0 (Input)
FCC1: RxD[2]
UTOPIA 16
1
2
FCC1: TxAddr[4]
MPHY, slave,
multiplexed polling
2
FCC1: TxClav3
MPHY, master, direct
polling
FCC2: TxAddr[0]
MPHY, slave,
multiplexed polling
1
2
FCC1: RxAddr[4]
MPHY, slave,
multiplexed polling
2
FCC1: RxClav3
MPHY, master, direct
polling
FCC2: RxAddr[0]
MPHY, slave,
multiplexed polling
FCC1: RxPrty
UTOPIA
TDM_C1: L1TSYNC/
3
GRANT
(secondary option)
FCC1: RxD[1]
UTOPIA 16
FCC1: RxD[0]
UTOPIA 16
3
FCC2: RxD[0]
UTOPIA 8
(secondary option)
3
FCC2: RxD[1]
UTOPIA 8
(secondary option)
MPC8260 PowerQUICC II UserÕs Manual
Pin Function
Default
PDIRD = 1 (Output)
Input
GND
GND
BRG1: BRGO
GND
GND
GND
GND
GND
GND
GND
BRG4: BRGO
BRG3: BRGO
PSORD = 1
PDIRD = 0 (Input, or
Default
Inout if SpeciÞed)
Input
3
TDM_A2: L1RSYNC
GND
(secondary option)
SPI: SPISEL
SPI: SPICLK
GND
Inout
SPI: SPIMOSI
Inout
SPI: SPIMISO
SPIMO
Inout
I2C: I2CSDA
Inout
I2C: I2CSCL
GND
Inout
TDM_B1: L1TXD
GND
Inout
TDM_B1: L1RXD
GND
Inout
TDM_B1: L1TSYNC/
GND
GRANT
TDM_B1: L1RSYNC
GND
FCC2: RxPrty
GND
UTOPIA
MOTOROLA
V
DD
V
DD
SI
V
DD
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