Features - Motorola MPC8260 PowerQUICC II User Manual

Part IV. Communications Processor Module
CPM Mux
BRGs
MCCs
Time-Slot Assigner
SIx
TDM Ax, Bx, Cx, Dx TDM Ax, Bx, Cx, Dx
Strobes
Figure 15-1. CPM Multiplexing Logic (CMX) Block Diagram

15.1 Features

The NMSI mode supports the following:
¥ Each FCC, SCC, and SMC can be programmed independently to work with a serial
deviceÕs own set of pins in a non-multiplexed manner.
¥ Each FCC can be connected to its own MII (media-independent interface).
¥ FCC1 can also be connected to an 8- or 16-bit ATM UTOPIA level-2 interface.
¥ FCC2 can also be connected also to an 8-bit ATM UTOPIA level-2 interface.
¥ Each SCC can have its own set of modem control pins.
¥ Each SMC can have its own set of four pins.
¥ Each FCC, SCC, and SMC can be driven from a bank of twenty clock pins or a bank
of eight BRGs.
15-2
Register Bus
SIx UTOPIA
Clock Address
Registers Register
(CMXSIxCR) (CMXUAR)
To Serials: SMC1
MUX MUX
SMC1
Clocks
Pins
MPC8260 PowerQUICC II UserÕs Manual
SMC
Clock
Register Register
(CMXSMR) (CMXSCR)
SMC2 SCC1 SCC2 SCC3
MUX MUX MUX MUX
SMC2 SCC1 SCC2 SCC3
Nonmultiplexed Serial Interface (NMSI) Pins
SCC FCC
Clock Clock
Register
(CMXFCR)
SCC4 FCC1 FCC2 FCC3
MUX MUX MUX MUX
SCC4 MII1/ MII2/
UTOPIA UTOPIA
8/16 8
MOTOROLA
MII3