Motorola MPC8260 PowerQUICC II User Manual page 796

Part IV. Communications Processor Module
4 bit 12 bit
PHY Addr VPI
0000
0000 00011111
0b00011
VPpointer
16 bit
VCI
00000111 11110000
VCpointer
15 bit
1 bit
Ñ
MS
Ch Code[15Ð0]
0
Figure 29-5. Address Compression Mechanism
Figure 29-5 shows VP_MASK selecting Þve VPI bits to index the VP-level table. The VP-
level table entry contains the 16-bit mask (VC_MASK) and the VC-level table offset
(VCOFFSET) for the next level of address mapping. The VC_MASK selects VCI bits 4Ð
10, which is used with VCT_BASE and VCOFFSET to indicate the received cellÕs channel
code.
Table 29-3. Field Descriptions for Address Compression
Field
PHY In multiple PHY mode, this Þeld contains the 4 least-signiÞcant bits of the current channelÕs physical
Addr address. Because this comparison Þeld is limited to 4 bits, two sets of look-up tables are needed if using
more than 16 PHYs.The msb of the PHY address lines (bit 4) selects between the two sets of tables. If the
msb is zero, the CP accesses the tables at VPT_BASE and VCT_BASE; if the msb is set, the CP uses
VPT1_BASE and VCT1_BASE. See Section 15.4.1, ÒCMX UTOPIA Address Register (CMXUAR).Ó
In single PHY mode, clear this Þeld.
VCI, VPI The VCI and VPI of the current channel.
Ch Code Pointer to internal or external connection table.
Ñ Reserved, should be cleared.
MS Match status.
0 Match was found.
1 Match was not found.
29-16
VP_MASK
VCT_BASE
16 bit
31
MPC8260 PowerQUICC II UserÕs Manual
VP-level addressing table
(in dual-port RAM recommended)
0
VPT_BASE
32-bit entries
16 bit
VC_MASK
VC-level addressing tables
(in external memory)
32-bit entries
Description
31
16 bit
VCOFFSET
MOTOROLA