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Part II. ConÞguration and Reset
The time-out period is calculated as follows:
This gives a range from 122 µs (PITC = 0x0000) to 8 seconds (PITC = 0xFFFF).
4.1.5 Software Watchdog Timer
The SIU provides the software watchdog timer option to prevent system lock in case the
software becomes trapped in loops with no controlled exit. Watchdog timer operations are
conÞgured in the SYPCR, described in Section 4.3.2.8, ÒSystem Protection Control
Register (SYPCR).Ó
The software watchdog timer is enabled after reset to cause a soft reset if it times out. If the
software watchdog timer is not needed, the user must clear SYPCR[SWE] to disable it. If
used, the software watchdog timer requires a special service sequence to be executed
periodically. Without this periodic servicing, the software watchdog timer times out and
issues a reset or a nonmaskable interrupt, programmed in SYPCR[SWRI]. Once software
writes SWRI, the state of SWE cannot be changed.
The software watchdog timer service sequence consists of the following two steps:
1. Write 0x556C to the software service register (SWSR)
2. Write 0xAA39 to SWSR
The service sequence clears the watchdog timer and the timing process begins again. If a
value other than 0x556C or 0xAA39 is written to the SWSR, the entire sequence must start
over. Although the writes must occur in the correct order before a time-out, any number of
instructions can be executed between the writes. This allows interrupts and exceptions to
occur between the two writes when necessary. Figure 4-6 shows a state diagram for the
watchdog timer.
Not 0x556C/DonÕt reload
Figure 4-6. Software Watchdog Timer Service State Diagram
4-6
PIT
=
-------------------------------------
period
F
Reset
State 0
Waiting for 0x556C
MPC8260 PowerQUICC II UserÕs Manual
PITC 1
+
PITC 1
+
=
-------------------------
8192
timersclk
0x556C/DonÕt reload
0xAA39/Reload
Not 0xAA39/DonÕt reload
State 1
Waiting for 0xAA39
MOTOROLA
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