Programming Six Ram Entries - Motorola MPC8260 PowerQUICC II User Manual

Part IV. Communications Processor Module
SI x RAM Address:
(16 Bits Wide)
Figure 14-6. One TDM Channel with Shadow RAM for Dynamic Route Change
This conÞguration should be chosen when only one TDM is needed, but dynamic rerouting
may be needed on that TDM. Similarly, for two TDM channels, the number of SI x RAM
entries are reduced for every TDM channel programmed for shadow mode.
14.4.3 Programming SI x RAM Entries
The programming of each entry in the SI x RAM determines the routing of the serial bits (or
bit groups) and the assertion of strobe outputs. If MCC is set, the entry refers to the
corresponding MCC; otherwise, it refers to other serial controllers. Figure 14-7 shows the
entry Þelds for both cases.
Bits 0 1
Field MCC = 0 SWTR
MCC = 1 LOOP/ECHO SUPER
R/W
Addr
When MCC = 0, the SI x RAM entry Þelds function as described in Table 14-1.
14-10
0
128 Entries
TXa
Route
255
1024
128 Entries
RXa
Route
1279
2 3 4
SSEL1 SSEL2 SSEL3 SSEL4
R/W
See Chapter 3, ÒMemory Map.Ó
Figure 14-7. SI x RAM Entry Fields
MPC8260 PowerQUICC II UserÕs Manual
Framing Signals
256
L1TCLKa x
L1TSYNCa x
511
1280
L1RCLKa x
L1RSYNCa x
1535
5 6 7 8 9 10 11 12 13
0 CSEL
MCSEL
14 15
CNT BYT LST
CNT BYT LST
MOTOROLA