Serial Interface Registers; Si Global Mode Registers (Sixgmr); Si Mode Registers (Sixmr) - Motorola MPC8260 PowerQUICC II User Manual

14.5 Serial Interface Registers

The serial interface registers are described in the following sections. The MCC
conÞguration registers, which deÞne the TDM mapping of the MCC channels, are
described in Section 27.8, ÒMCC ConÞguration Registers (MCCFx).Ó Note that the
programming of SI registers and SI x RAM must be coherent with the MCCF programming.
14.5.1 SI Global Mode Registers (SI xGMR)
The SI global mode registers (SIxGMR), shown in Figure 14-10, deÞnes the activation state
of the TDM channels for each SI.
Bits 0
Field STZD
Reset
R/W
Addr
Figure 14-10. SI Global Mode Registers (SIxGMR)
Table 14-4 describes SIxGMR.
Bit Name
0Ð3 STZx Program L1TXDx to zero for TDM a, b, c or d
0 Normal operation
1 L1TXDx = 0 until serial clocks are available, which is useful for GCI activation. See Section 14.7.1,
ÒSI GCI Activation/Deactivation Procedure.Ó
4Ð7 ENx Enable TDMx. Note that enabling a TDM is the last step in initialization.
0 TDM channel x is disabled. The SIx RAMs and routing for TDMx are in a state of reset, but all other
SI functions still operate.
1 All TDMx functions are enabled.

14.5.2 SI Mode Registers (SIxMR)

There are eight SI mode registers (SIxMR), shown in Figure 14-11, one for each TDM
channel (SIxAMR, SIxBMR, SIxCMR, and SIxDMR). They are used to deÞne SI operation
modes and allow the user (with SIx RAM) to support any or all of the ISDN channels
independently when in IDL or GCI mode. Any extra serial channel can then be used for
other purposes.
MOTOROLA
1 2
STZC STZB
0x11B28 (SI1GMR), 0x11B48 (SI2GMR)
Table 14-4. SIxGMR Field Descriptions
Chapter 14. Serial Interface with Time-Slot Assigner
Part IV. Communications Processor Module
3 4
STZA END
0000_0000
R/W
Description
5 6
ENC ENB
7
ENA
14-17