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Table 10-35 describes RAM word Þelds.
Bit
Name
0
CST1 Chip-select timing 1. DeÞnes the state of CS during clock phase 1.
0 The value of the CS line at the rising edge of T1 will be 0
1 The value of the CS line at the rising edge of T1 will be 1
See Section 10.6.4.1.1, ÒChip-Select Signals (CxTx).Ó
1
CST2 Chip-select timing 2. DeÞnes the state of CS during clock phase 2.
0 The value of the CS line at the rising edge of T2 will be 0
1 The value of the CS line at the rising edge of T2 will be 1
2
CST3 Chip-select timing 3. DeÞnes the state of CS during clock phase 3.
0 The value of the CS line at the rising edge of T3 will be 0
1 The value of the CS line at the rising edge of T3 will be 1
3
CST4 Chip-select timing4. DeÞnes the state of CS during clock phase 4.
0 The value of the CS line at the rising edge of T4 will be 0
1 The value of the CS line at the rising edge of T4 will be 1
4
BST1 Byte-select timing 1. DeÞnes the state of BS during clock phase 1.
0 The value of the BS lines at the rising edge of T2 will be 0
1 The value of the BS lines at the rising edge of T2 will be 1
The Þnal value of the BS lines depends on the values of BRx[PS], the TSIZ lines, and A[30Ð31] for
the access. See Section 10.6.4.1.2, ÒByte-Select Signals (BxTx).Ó
5
BST2 Byte-select timing 2. DeÞnes the state of BS during clock phase 2.
0 The value of the BS lines at the rising edge of T2 will be 0
1 The value of the BS lines at the rising edge of T2 will be 1
The Þnal value of the BS lines depends on the values of BRx[PS], TSIZx, and A[30Ð31] for the
access.
6
BST3 Byte-select timing 3. DeÞnes the state of BS during clock phase 3.
0 The value of the BS lines at the rising edge of T3 will be 0
1 The value of the BS lines at the rising edge of T3 will be 1
The Þnal value of the BS lines depends on the values of BRx[PS], TSIZx, and A[30Ð31] for the
access.
7
BST4 Byte-select timing 4. DeÞnes the state of BS during clock phase 4.
0 The value of the BS lines at the rising edge of T4 will be 0
1 The value of the BS lines at the rising edge of T4 will be 1
The Þnal value of the BS lines depends on the values of BRx[PS], TSIZx, and A[30Ð31] for the
access.
8Ð9
G0L
General-purpose line 0 lower. DeÞnes the state of GPL0 during phases 1Ð2.
00 The value of GPL0 at the rising edge of T1 is as deÞned in MxMR[G0CL]
10 The value of the GPL0 line at the rising edge of T1 will be 0
11 The value of the GPL0 line at the rising edge of T1 will be 1
See Section 10.6.4.1.3, ÒGeneral-Purpose Signals (GxTx, GOx).Ó
10Ð11
G0H
General-purpose line 0 higher. DeÞnes the state of GPL0 during phase 3Ð4.
00 The value of GPL0 at the rising edge of T3 is as deÞned in MxMR[G0CL]
10 The value of the GPL0 line at the rising edge of T3 will be 0
11 The value of the GPL0 line at the rising edge of T3 will be 1
See Section 10.6.4.1.3, ÒGeneral-Purpose Signals (GxTx, GOx).Ó
MOTOROLA
Table 10-35. RAM Word Bit Settings
Chapter 10. Memory Controller
Part III. The Hardware Interface
Description
10-71
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