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System Bus (ROM and RAM)
ASYNC
SMC1
SCC1
Ethernet
PHY
The MPC8260 can identify and support each IDL channel or can output strobe lines for
interfacing devices that do not support the IDL bus. The IDL signals for each transmit and
receive channel are described in Table 14-9.
Signal
L1RCLKx
IDL clock; input to the MPC8260.
L1RSYNCx IDL sync signal; input to the MPC8260. This signal indicates that the clock periods following the pulse
designate the IDL frame.
L1RXDx
IDL receive data; input to the MPC8260. Valid only for the bits supported by the IDL; ignored for any
other signals present.
L1TXDx
IDL transmit data; output from the MPC8260. Valid only for the bits that are supported by the IDL;
otherwise, three-stated.
L1RQx
IDL request permission to transmit on the D channel; output from the MPC8260 on the L1RQx pin.
L1GRx
IDL grant permission to transmit on the D Channel; input to the MPC8260 on the L1TSYNCx pin.
Note: x = a, b, c, and d for TDMa, TDMb, TDMc, and TDMd (for SI1 and SI2).
MOTOROLA
SPI
MPC8260
SMC2
(Data)
SCC2
TSA
SCC3
B2+D
Ethernet
LAN
Figure 14-22. IDL Terminal Adaptor
Table 14-9. IDL Signal Descriptions
Chapter 14. Serial Interface with Time-Slot Assigner
Part IV. Communications Processor Module
CODEC/Filter
Monocircuit
B1
IDL
ICL
(Control)
B1+B2+D
Description
PCM
POTS
S/T
4 wire
Transceiver
14-27
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