Motorola MPC8260 PowerQUICC II User Manual page 278

Part III. The Hardware Interface
The MPC8260 supports the following new features as compared to the MPC860 and
MPC850.
¥ The synchronous DRAM machine enables back-to-back memory read or write
operations using page mode, pipelined operation and bank interleaving for
high-performance systems.
¥ The memory controller supports the local bus and the 60x bus in parallel. The 60x
bus and the local bus share twelve memory banks as well as two SDRAM machines,
three user-programmable machines (UPMs) and GPCMs.
¥ The memory controller supports atomic operation.
¥ The memory controller supports read-modify-write (RMW) data parity check.
¥ The memory controller supports ECC data check and correction.
¥ Two data buffer controls (one for the local bus).
¥ ECC/parity byte select pin, which enables a fast, glueless connection to ECC/
RMW-parity devices.
¥ 18-bit address and 32-bit local data bus memory controller. The local bus memory
controller supports the following:
Ñ 8-, 16-, and 32-bit port sizes
Ñ Parity checking and generation
Ñ Ability to work in parallel with the 60x bus memory controller
Unless stated otherwise, this chapter describes the 60x bus memory controller. The
local bus memory controller provides the same functionality as the 60x bus memory
controller except 64-bit port size, ECC, and external master support.
¥ Flexible chip-select assignmentÑThe 60x bus and local bus share twelve
chip-select lines (controlled by a memory controller bank). The user can allocate the
twelve banks as needed between the 60x bus and the local bus.
¥ Flexible UPM assignmentÑThe user can assign any of the three UPMs to the 60x
bus or the Local bus
Figure 10-1 shows the dual-bus architecture.
10-2 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA