Brc Performance Calculations - Motorola MPC8260 PowerQUICC II User Manual

Part IV. Communications Processor Module
512 User Cells
3
FMC Cell Data Cell
TUC0
TUC0+1
BEDC
TSTP

29.6.6.4 BRC Performance Calculations

BRC reception uses the regular AAL0 raw cell queue. On receiving two consecutive BRC
cells, the management layer can calculate the following:
¥ The difference between two TUCs (Nt)
¥ The difference between two TRCCs (Nr)
Information about the connection can be gained by comparing Nt and Nr:
¥ If Nt > Nr, the difference indicates the number of lost cells of this block test.
¥ If Nt < Nr, the difference indicates the number of misinserted cells of this block test.
¥ When Nt = Nr, no cells are lost or misinserted.
29.7 User-DeÞned Cells (UDC)
Typical ATM cells are 53 bytes long and consist of a 4-byte header, 1-byte HEC, and 48-
byte payload. The MPC8260 also supports user-deÞned cells with up to 12 bytes of extra
header Þelds for internal information for switching applications. This choice is made during
initialization by writing to the FPSMR; see Section 29.13.2, ÒFCC Protocol-SpeciÞc Mode
Register (FPSMR).Ó As shown in Figure 29-19, the extra header size can vary between 1 to
12 bytes (byte resolution) and the HEC octet is optional.
29-32
2
Data Cell FMC Cell Data Cell
TUC0
TUC0+1
BEDC
TSTP
Destination BRCÕs
Transmit Stream
BRC Cell
TUC0
TUC0+1
TRCC0
TRCC0+1
BLER
TSTP
Figure 29-18. FMC, BRC Insertion
MPC8260 PowerQUICC II UserÕs Manual
512 User Cells
Data Cell
2
1
BRC Cell
TUC0
TUC0+1
TRCC0
TRCC0+1
BLER
TSTP
1
Source Cells
Stream
FMC Cell
TUC0
TUC0+1
BEDC
TSTP
3
BRC Cell
TUC0
TUC0+1
TRCC0
TRCC0+1
BLER
TSTP
MOTOROLA