Idma Performance; Idma Event Register (Idsr) And Mask Register (Idmr) - Motorola MPC8260 PowerQUICC II User Manual

Part IV. Communications Processor Module
Table 18-8. Valid STS/DTS Values for Peripherals (Continued)
DMA_WRAP Internal Buffer Size SS_MAX
011 512
100 1024
101 2048
1
These values come out as a single transaction on the bus.
2
Peripherals that can accept bursts of 32 bytes are supported.

18.8.3 IDMA Performance

The transfer parameters STS, DTS, SS_MAX, and DMA_WRAP determine the amount of
data transferred for each
transfer buffers and the maximum transfer sizes allows longer transfers to memory devices,
optimizes bus usage and thus reduces the overall load on the CP.
For example, 2,016 bytes can be transferred by issuing one
2-Kbyte internal transfer buffer, or by issuing 63
buffer. The load on the CP in the second case is about 63 times more than the Þrst.

18.8.4 IDMA Event Register (IDSR) and Mask Register (IDMR)

The IDMA event (status) register (IDSR) is used to report events recognized by the IDMA
controller. On recognition of an event, the controller sets the corresponding IDSR bit. Each
IDMA event bit can generate a maskable interrupt to the core. Even bits are cleared by
writing ones; writing zeros has no effect.
The IDMA mask register (IDMR) has the same format as IDSR. Setting IDMR bits enables,
and clearing IDMR bits disables, the corresponding interrupts in the event register.
Figure 18-9 shows the bit format for IDSR and IDMR.
18-22
S/D Mode
15 * 32 01
10
31 * 32 01
10
63 * 32 01
10
_ command issued. Using large internal IDMA
START IDMA
MPC8260 PowerQUICC II UserÕs Manual
STS (in Bytes)
15 * 32
1, 2, 4, 8 (single); 32
(burst)
31 * 32
1, 2, 4, 8 (single); 32
(burst)
63 * 32
1, 2, 4, 8 (single); 32
(burst)
_
START IDMA
_ commands using a 64-byte
START IDMA
DTS (in Bytes)
1, 2, 4, 8 (single); 32
(burst)
15 * 32
1, 2, 4, 8 (single); 32
(burst)
31 * 32
1, 2, 4, 8 (single); 32
(burst)
63 * 32
command using a
MOTOROLA