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10.9 External Master Support (60x-Compatible Mode)
The memory controller supports internal and external bus masters. Accesses from the core
or the CPM are considered internal; accesses from an external bus master are external.
External bus master support is available only if the MPC8260 is placed in 60x-compatible
mode. This is done by setting the BCR[EBM], described in Section 4.3.2.1, ÒBus
ConÞguration Register (BCR).Ó
There are two types of external bus masters:
¥ Any 60x-compatible device that uses a 64-bit data bus, such as: MPC603e,
MPC604e, MPC750, MPC2605 (L2 cache) in copy-back mode and others
¥ MPC8260 type devices
10.9.1 60x-Compatible External Masters
Any 60x-compatible devices that use a 64-bit data bus can access the MPC8260 internal
registers and local bus. These devices can also use memory controller services under the
following restrictions, which apply only to 60x-assigned memory banks accessed by the
external device:
¥ 64-bit port size only
¥ No ECC or RMW-parity
For 60x bus compatibility, the following connections should be observed:
¥ MPC8260Õs TSIZ[1Ð3] should be connected to the external masterÕs TSIZ[0Ð2]
¥ MPC8260Õs TSIZ[0] should be pulled down
¥ MPC8260Õs PSDVAL should be pulled up
10.9.2 MPC8260-Type External Masters
An MPC8260 external master is a 60x-compatible master with additional functionality. As
described in the following, it has fewer the restrictions than other 60x-compatible masters:
¥ Any port size is allowed
¥ ECC and RMW-parity are supported
10.9.3 Extended Controls in 60x-Compatible Mode
In 60x-compatible mode, the memory controller provided extended controls for the glue
logic. The extended control consists of the following:
¥ Memory address latch (ALE) to latch the 60x address for memory use
¥ The address multiplex pin (GPL5/SDAMUX), which controls external multiplexing
for DRAM and SDRAM devices
¥ LSB address pins (BADDR[27Ð31]) for incrementing memory addresses
MOTOROLA
Chapter 10. Memory Controller
Part III. The Hardware Interface
10-101
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