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Part IV. Communications Processor Module
Ethernet controller then waits for a new frame. The Ethernet controller receives serial data
least-signiÞcant nibble Þrst.
30.6 Flow Control
Because collisions cannot occur in full-duplex mode, Fast Ethernet can operate at the
maximum rate. When the rate becomes too fast for a stationÕs receiver, the stationÕs
transmitter can send ßow-control frames to reduce the rate. Flow-control instructions are
transferred by special frames of minimum frame size. The length/type Þelds of these frames
have a special value. Table 30-1 shows the ßow-control frame structure.
Size [Octets]
Description
7
Preamble
1
SFD
6
Destination address
6
Source address
2
Length/type
2
MAC opcode
2
MAC parameter
42
Reserved
4
FCS
When ßow-control mode is enabled (FPSMRx[FCE]) and the receiver identiÞes a pause-
ßow control frame sent to individual or broadcast addresses, transmission stops for the time
speciÞed in the control frame. During this pause, only the out-of-sequence frame is sent.
Normal transmission resumes after the pause timer stops counting. If another pause-control
frame is received during the pause, the period changes to the new value received.
30.7 CAM Interface
The MPC8260 internal address recognition logic can be used in combination with an
external CAM. When using a CAM, the FCC must be in promiscuous mode
(FPSMRx[PRO] = 1). See Section 30.12, ÒEthernet Address Recognition.Ó
The Ethernet controller writes two 32-bit accesses to the CAM and then reads the result in
a 32-bit access. If the high bit of the result is set, the frame is rejected; otherwise, the lower
16 bits are attached to the end of the frame.
30-8
Table 30-1. Flow Control Frame Structure
Value
01-80C2-00-00-01
88-08
00-01
Ñ
MPC8260 PowerQUICC II UserÕs Manual
Comment
Start frame delimiter
Multicast address reserved for use in MAC frames
Control frame type
Pause command
Pause period measured in slot times, most-
signiÞcant octet Þrst
Frame check sequence (CRC)
MOTOROLA
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