Motorola MPC8260 PowerQUICC II User Manual page 320

Part III. The Hardware Interface
Deactivate
CLK
ALE
CS
SDRAS
SDCAS
BS
*
A10 = 1
MA[0Ð11] Z
WE
DQM
Data
* BSÑBank select according to SDRAM organization. A10 = 1 means not all banks will be precharged.
CAS Latency = 3
Figure 10-31. SDRAM Four-Beat Burst Read, Page Miss, CL = 3
CLK
ALE
CS
SDRAS
SDCAS
MA[0Ð11]
WE
DQM
Data
Figure 10-32. SDRAM Single-Beat Write, Page Hit
CLK
ALE
CS
SDRAS
SDCAS
MA[0Ð11] Row
WE
DQM
Data
Figure 10-33. SDRAM Three-Beat Burst Write, Page Closed
10-44
Activate
Row
Column
D0
Column
D0 D1 D2
MPC8260 PowerQUICC II UserÕs Manual
Col
D0 D2
D1 D4
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