Table of Contents
Advertisement
Part IV. Communications Processor Module
In external request mode (ERM = 1),
peripheral asserting DONE.
Note: In memory-to-peripheral, peripheral-to-memory, and ßy-by modes, if a
command is issued with no data in the internal buffer, the BD is immediately closed and the
channel is stopped. In this case, a peripheral expecting DONE to be asserted is not notiÞed
because the last transfer of the buffer (with BD[DDN or SDN] set) is not performed.
18.10 IDMA Bus Exceptions
Bus exceptions can occur while the IDMA has the bus and is transferring operands. In any
computer system, a hardware failure can cause an error during a bus transaction due to
random noise or an illegal access. When a synchronous bus structure (like those supported
by the MPC8260) is used, it is easy to make provisions for a bus master to detect and
respond to errors during a bus transaction. The IDMA recognizes the same bus exceptions
as the core, reset and transfer error, as described in Table 18-11.
Exception
Reset
On an external reset, the IDMA immediately aborts the channel operation, returns to the idle state, and
clears IDSR. If reset is detected when a bus transaction is in progress, the transaction is terminated, the
control and address/data pins are three-stated, and bus mastership is released.
Transfer
When a fatal error occurs during a bus transaction, a bus error exception is used to abort the transaction
Error
and systematically terminate channel operation. The IDMA terminates the current bus transaction,
signals an error in the SDSR, and signals an interrupt if the corresponding bit in the SDMR is set. The
CPM must be reset before IDMA operation is restarted. Any data previously read from the source into the
internal storage is lost, however, issuing a
Note: Any source or destination device for an operand under IDMA handshake control for single-address
transfers may need to monitor TEA to detect a bus exception for the current bus transaction. TEA
terminates the transaction immediately and negates DACK, which is used to control the transfer to/from
the device.
18.10.1 Externally Recognizing IDMA Operand Transfers
The following ways can be used determine externally that the IDMA is executing a bus
transaction:
¥ The TC[2] signal (programmed in DCM[TC2]) or SDMA channels can be
programmed to a unique code that identiÞes an IDMA transfer.
¥ The DACK signal shows accesses to the peripheral device. DACK activates on either
the source or destination bus transactions, depending on DCM[S/D].
18-27
_
STOP
IDMA
Table 18-11. IDMA Bus Exceptions
Description
START
MPC8260 PowerQUICC II UserÕs Manual
command processing has priority over a
_
command transfers the last BD again.
IDMA
_
STOP
IDMA
MOTOROLA
Advertisement
Table of Contents
